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   <div id="projectname">Kinetis Bootloader
   &#160;<span id="projectnumber">2.0.0</span>
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   <div id="projectbrief">Common bootloader for Kinetis devices</div>
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<div class="title">system_MKL43Z4.h</div>  </div>
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<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00002"></a><span class="lineno">    2</span>&#160;<span class="comment">** ###################################################################</span></div><div class="line"><a name="l00003"></a><span class="lineno">    3</span>&#160;<span class="comment">**     Processors:          MKL43Z256VLH4</span></div><div class="line"><a name="l00004"></a><span class="lineno">    4</span>&#160;<span class="comment">**                          MKL43Z128VLH4</span></div><div class="line"><a name="l00005"></a><span class="lineno">    5</span>&#160;<span class="comment">**                          MKL43Z64VLH4</span></div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">**                          MKL43Z256VMP4</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment">**                          MKL43Z128VMP4</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment">**                          MKL43Z64VMP4</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment">**     Compilers:           Keil ARM C/C++ Compiler</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment">**                          Freescale C/C++ for Embedded ARM</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment">**                          GNU C Compiler</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment">**                          GNU C Compiler - CodeSourcery Sourcery G++</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment">**                          IAR ANSI C/C++ Compiler for ARM</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment">**     Reference manual:    KL43P64M48SF6RM, Rev.3, Aug 2014</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment">**     Version:             rev. 1.5, 2014-09-05</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment">**     Build:               b141218</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment">**     Abstract:</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment">**         Provides a system configuration function and a global variable that</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment">**         contains the system frequency. It configures the device and initializes</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment">**         the oscillator (PLL) that is part of the microcontroller device.</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment">**     Copyright (c) 2014 Freescale Semiconductor, Inc.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment">**     All rights reserved.</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment">**     Redistribution and use in source and binary forms, with or without modification,</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment">**     are permitted provided that the following conditions are met:</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment">**     o Redistributions of source code must retain the above copyright notice, this list</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment">**       of conditions and the following disclaimer.</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment">**     o Redistributions in binary form must reproduce the above copyright notice, this</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment">**       list of conditions and the following disclaimer in the documentation and/or</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment">**       other materials provided with the distribution.</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment">**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment">**       contributors may be used to endorse or promote products derived from this</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment">**       software without specific prior written permission.</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="comment">**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS &quot;AS IS&quot; AND</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="comment">**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;<span class="comment">**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR</span></div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="comment">**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="comment">**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;<span class="comment">**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT</span></div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="comment">**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="comment">**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;<span class="comment">**     http:                 www.freescale.com</span></div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="comment">**     mail:                 support@freescale.com</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="comment">**     Revisions:</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">**     - rev. 1.0 (2014-03-27)</span></div><div class="line"><a name="l00058"></a><span class="lineno">   58</span>&#160;<span class="comment">**         Initial version.</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">**     - rev. 1.1 (2014-05-26)</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">**         I2S registers TCR2/RCR2 and others were changed.</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="comment">**         FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="comment">**         Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.:</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="comment">*FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="comment">**         Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="comment">**         Clock configuration for high range external oscillator has been added.</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="comment">**         RFSYS module access has been added.</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="comment">**     - rev. 1.2 (2014-07-10)</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="comment">**         GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="comment">**         UART0 - UART0 module renamed to UART2.</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="comment">**         I2S - removed MDR register.</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="comment">**     - rev. 1.3 (2014-08-21)</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="comment">**         UART2 - Removed ED register.</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;<span class="comment">**         UART2 - Removed MODEM register.</span></div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;<span class="comment">**         UART2 - Removed IR register.</span></div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">**         UART2 - Removed PFIFO register.</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;<span class="comment">**         UART2 - Removed CFIFO register.</span></div><div class="line"><a name="l00077"></a><span class="lineno">   77</span>&#160;<span class="comment">**         UART2 - Removed SFIFO register.</span></div><div class="line"><a name="l00078"></a><span class="lineno">   78</span>&#160;<span class="comment">**         UART2 - Removed TWFIFO register.</span></div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;<span class="comment">**         UART2 - Removed TCFIFO register.</span></div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;<span class="comment">**         UART2 - Removed RWFIFO register.</span></div><div class="line"><a name="l00081"></a><span class="lineno">   81</span>&#160;<span class="comment">**         UART2 - Removed RCFIFO register.</span></div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;<span class="comment">**         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.</span></div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;<span class="comment">**         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.</span></div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;<span class="comment">**         SIM - Removed bitfield DIEID in SDID register.</span></div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;<span class="comment">**     - rev. 1.4 (2014-09-01)</span></div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;<span class="comment">**         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.</span></div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;<span class="comment">**         USB - USB0_CTL1 was renamed to USB0_CTL register.</span></div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;<span class="comment">**     - rev. 1.5 (2014-09-05)</span></div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;<span class="comment">**         USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.</span></div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;<span class="comment">**</span></div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;<span class="comment">** ###################################################################</span></div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;</div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;<span class="preprocessor">#ifndef _SYSTEM_MKL43Z4_H_</span></div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;<span class="preprocessor">#define _SYSTEM_MKL43Z4_H_ </span></div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;</div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;</div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;<span class="preprocessor">#ifndef DISABLE_WDOG</span></div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;<span class="preprocessor">#define DISABLE_WDOG 1</span></div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;</div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;<span class="preprocessor">#define ACK_ISOLATION 1</span></div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;</div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;<span class="comment">/* MCG_Lite mode constants */</span></div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;</div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;<span class="preprocessor">#define MCG_MODE_LIRC_8M 0U</span></div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;<span class="preprocessor">#define MCG_MODE_HIRC 1U</span></div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;<span class="preprocessor">#define MCG_MODE_LIRC_2M 2U</span></div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;<span class="preprocessor">#define MCG_MODE_EXT 3U</span></div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;</div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;<span class="comment">/* Predefined clock setups</span></div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;<span class="comment">   0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode</span></div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;<span class="comment">         Default part configuration.</span></div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;<span class="comment">         Core clock/Bus clock derived from the internal clock source 8 MHz</span></div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;<span class="comment">         Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for</span></div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;<span class="comment">   derivatived with USB)</span></div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;<span class="comment">   1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode</span></div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;<span class="comment">         Maximum achievable clock frequency configuration using internal clock.</span></div><div class="line"><a name="l00135"></a><span class="lineno">  135</span>&#160;<span class="comment">         Core clock/Bus clock derived from the internal clock source 48MHz</span></div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;<span class="comment">         Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for</span></div><div class="line"><a name="l00137"></a><span class="lineno">  137</span>&#160;<span class="comment">   derivatived with USB)</span></div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;<span class="comment">   2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode</span></div><div class="line"><a name="l00139"></a><span class="lineno">  139</span>&#160;<span class="comment">         Core clock/Bus clock derived directly from the external crystal 32.768kHz</span></div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;<span class="comment">         The clock settings is ready for Very Low Power Run mode.</span></div><div class="line"><a name="l00141"></a><span class="lineno">  141</span>&#160;<span class="comment">         Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable</span></div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;<span class="comment">   only for derivatived with USB)</span></div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;<span class="comment">   3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode</span></div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;<span class="comment">         Core clock/Bus clock derived from the internal clock source 2 MHz</span></div><div class="line"><a name="l00145"></a><span class="lineno">  145</span>&#160;<span class="comment">         The clock settings is ready for Very Low Power Run mode.</span></div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;<span class="comment">         Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for</span></div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;<span class="comment">   derivatived with USB)</span></div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;<span class="comment">   4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode</span></div><div class="line"><a name="l00149"></a><span class="lineno">  149</span>&#160;<span class="comment">         USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.</span></div><div class="line"><a name="l00150"></a><span class="lineno">  150</span>&#160;<span class="comment">         Core clock/Bus clock derived from the internal clock source 48MHz</span></div><div class="line"><a name="l00151"></a><span class="lineno">  151</span>&#160;<span class="comment">         Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)</span></div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;<span class="comment">   5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode</span></div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;<span class="comment">         Core clock/Bus clock derived directly from the external crystal 8 MHz</span></div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;<span class="comment">         Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for</span></div><div class="line"><a name="l00155"></a><span class="lineno">  155</span>&#160;<span class="comment">   derivatived with USB)</span></div><div class="line"><a name="l00156"></a><span class="lineno">  156</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00157"></a><span class="lineno">  157</span>&#160;</div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;<span class="comment">/* Define clock source values */</span></div><div class="line"><a name="l00159"></a><span class="lineno">  159</span>&#160;</div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;<span class="preprocessor">#define CPU_XTAL_CLK_HZ 32768u        </span><span class="comment">/* Value of the external crystal or oscillator clock frequency in Hz */</span><span class="preprocessor"></span></div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;<span class="preprocessor">#define CPU_INT_FAST_CLK_HZ 48000000u </span><span class="comment">/* Value of the fast internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;<span class="preprocessor">#define CPU_INT_IRC_CLK_HZ 48000000u  </span><span class="comment">/* Value of the 48M internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00163"></a><span class="lineno">  163</span>&#160;</div><div class="line"><a name="l00164"></a><span class="lineno">  164</span>&#160;<span class="comment">/* Low power mode enable */</span></div><div class="line"><a name="l00165"></a><span class="lineno">  165</span>&#160;<span class="comment">/* SMC_PMPROT: AVLP=1,AVLLS=1 */</span></div><div class="line"><a name="l00166"></a><span class="lineno">  166</span>&#160;<span class="preprocessor">#define SYSTEM_SMC_PMPROT_VALUE 0x2Au </span><span class="comment">/* SMC_PMPROT */</span><span class="preprocessor"></span></div><div class="line"><a name="l00167"></a><span class="lineno">  167</span>&#160;</div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;<span class="preprocessor">#ifdef CLOCK_SETUP</span></div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;<span class="preprocessor">#if (CLOCK_SETUP == 0)</span></div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;<span class="preprocessor">#define DEFAULT_SYSTEM_CLOCK 4000000u </span><span class="comment">/* Default System clock value */</span><span class="preprocessor"></span></div><div class="line"><a name="l00171"></a><span class="lineno">  171</span>&#160;<span class="preprocessor">#define CPU_INT_SLOW_CLK_HZ 8000000u  </span><span class="comment">/* Value of the slow internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00172"></a><span class="lineno">  172</span>&#160;<span class="preprocessor">#define MCG_MODE MCG_MODE_LIRC_8M     </span><span class="comment">/* Clock generator mode */</span><span class="preprocessor"></span></div><div class="line"><a name="l00173"></a><span class="lineno">  173</span>&#160;<span class="comment">/* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */</span></div><div class="line"><a name="l00174"></a><span class="lineno">  174</span>&#160;<span class="preprocessor">#define MCG_C1_VALUE 0x42u </span><span class="comment">/* MCG_C1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00175"></a><span class="lineno">  175</span>&#160;<span class="comment">/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */</span></div><div class="line"><a name="l00176"></a><span class="lineno">  176</span>&#160;<span class="preprocessor">#define MCG_C2_VALUE 0x01u </span><span class="comment">/* MCG_C2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00177"></a><span class="lineno">  177</span>&#160;<span class="comment">/* MCG_SC: FCRDIV=0 */</span></div><div class="line"><a name="l00178"></a><span class="lineno">  178</span>&#160;<span class="preprocessor">#define MCG_SC_VALUE 0x00u </span><span class="comment">/* MCG_SC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00179"></a><span class="lineno">  179</span>&#160;<span class="comment">/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */</span></div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;<span class="preprocessor">#define MCG_MC_VALUE 0x00u </span><span class="comment">/* MCG_MC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00181"></a><span class="lineno">  181</span>&#160;<span class="comment">/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */</span></div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;<span class="preprocessor">#define OSC0_CR_VALUE 0x00u </span><span class="comment">/* OSC0_CR */</span><span class="preprocessor"></span></div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;<span class="comment">/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */</span></div><div class="line"><a name="l00184"></a><span class="lineno">  184</span>&#160;<span class="preprocessor">#define SMC_PMCTRL_VALUE 0x00u </span><span class="comment">/* SMC_PMCTRL */</span><span class="preprocessor"></span></div><div class="line"><a name="l00185"></a><span class="lineno">  185</span>&#160;<span class="comment">/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */</span></div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u </span><span class="comment">/* SIM_CLKDIV1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;<span class="comment">/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */</span></div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u </span><span class="comment">/* SIM_SOPT1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00189"></a><span class="lineno">  189</span>&#160;<span class="comment">/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */</span></div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u </span><span class="comment">/* SIM_SOPT2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;<span class="preprocessor">#elif(CLOCK_SETUP == 1)</span></div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;<span class="preprocessor">#define DEFAULT_SYSTEM_CLOCK 48000000u    </span><span class="comment">/* Default System clock value */</span><span class="preprocessor"></span></div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;<span class="preprocessor">#define CPU_INT_SLOW_CLK_HZ 8000000u      </span><span class="comment">/* Value of the slow internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;<span class="preprocessor">#define MCG_MODE MCG_MODE_HIRC            </span><span class="comment">/* Clock generator mode */</span><span class="preprocessor"></span></div><div class="line"><a name="l00195"></a><span class="lineno">  195</span>&#160;<span class="comment">/* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */</span></div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;<span class="preprocessor">#define MCG_C1_VALUE 0x00u                </span><span class="comment">/* MCG_C1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00197"></a><span class="lineno">  197</span>&#160;<span class="comment">/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */</span></div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;<span class="preprocessor">#define MCG_C2_VALUE 0x01u                </span><span class="comment">/* MCG_C2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;<span class="comment">/* MCG_SC: FCRDIV=0 */</span></div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;<span class="preprocessor">#define MCG_SC_VALUE 0x00u                </span><span class="comment">/* MCG_SC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00201"></a><span class="lineno">  201</span>&#160;<span class="comment">/* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */</span></div><div class="line"><a name="l00202"></a><span class="lineno">  202</span>&#160;<span class="preprocessor">#define MCG_MC_VALUE 0x80u                </span><span class="comment">/* MCG_MC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00203"></a><span class="lineno">  203</span>&#160;<span class="comment">/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */</span></div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;<span class="preprocessor">#define OSC0_CR_VALUE 0x00u               </span><span class="comment">/* OSC0_CR */</span><span class="preprocessor"></span></div><div class="line"><a name="l00205"></a><span class="lineno">  205</span>&#160;<span class="comment">/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */</span></div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="preprocessor">#define SMC_PMCTRL_VALUE 0x00u            </span><span class="comment">/* SMC_PMCTRL */</span><span class="preprocessor"></span></div><div class="line"><a name="l00207"></a><span class="lineno">  207</span>&#160;<span class="comment">/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */</span></div><div class="line"><a name="l00208"></a><span class="lineno">  208</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u </span><span class="comment">/* SIM_CLKDIV1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00209"></a><span class="lineno">  209</span>&#160;<span class="comment">/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */</span></div><div class="line"><a name="l00210"></a><span class="lineno">  210</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u </span><span class="comment">/* SIM_SOPT1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00211"></a><span class="lineno">  211</span>&#160;<span class="comment">/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */</span></div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT2_VALUE 0x03000000U </span><span class="comment">/* SIM_SOPT2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;<span class="preprocessor">#elif(CLOCK_SETUP == 2)</span></div><div class="line"><a name="l00214"></a><span class="lineno">  214</span>&#160;<span class="preprocessor">#define DEFAULT_SYSTEM_CLOCK 32768u    </span><span class="comment">/* Default System clock value */</span><span class="preprocessor"></span></div><div class="line"><a name="l00215"></a><span class="lineno">  215</span>&#160;<span class="preprocessor">#define CPU_INT_SLOW_CLK_HZ 8000000u   </span><span class="comment">/* Value of the slow internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00216"></a><span class="lineno">  216</span>&#160;<span class="preprocessor">#define MCG_MODE MCG_MODE_EXT          </span><span class="comment">/* Clock generator mode */</span><span class="preprocessor"></span></div><div class="line"><a name="l00217"></a><span class="lineno">  217</span>&#160;<span class="comment">/* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */</span></div><div class="line"><a name="l00218"></a><span class="lineno">  218</span>&#160;<span class="preprocessor">#define MCG_C1_VALUE 0x82u             </span><span class="comment">/* MCG_C1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00219"></a><span class="lineno">  219</span>&#160;<span class="comment">/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */</span></div><div class="line"><a name="l00220"></a><span class="lineno">  220</span>&#160;<span class="preprocessor">#define MCG_C2_VALUE 0x05u             </span><span class="comment">/* MCG_C2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00221"></a><span class="lineno">  221</span>&#160;<span class="comment">/* MCG_SC: FCRDIV=0 */</span></div><div class="line"><a name="l00222"></a><span class="lineno">  222</span>&#160;<span class="preprocessor">#define MCG_SC_VALUE 0x00u             </span><span class="comment">/* MCG_SC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00223"></a><span class="lineno">  223</span>&#160;<span class="comment">/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */</span></div><div class="line"><a name="l00224"></a><span class="lineno">  224</span>&#160;<span class="preprocessor">#define MCG_MC_VALUE 0x00u             </span><span class="comment">/* MCG_MC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00225"></a><span class="lineno">  225</span>&#160;<span class="comment">/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */</span></div><div class="line"><a name="l00226"></a><span class="lineno">  226</span>&#160;<span class="preprocessor">#define OSC0_CR_VALUE 0x80u            </span><span class="comment">/* OSC0_CR */</span><span class="preprocessor"></span></div><div class="line"><a name="l00227"></a><span class="lineno">  227</span>&#160;<span class="comment">/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */</span></div><div class="line"><a name="l00228"></a><span class="lineno">  228</span>&#160;<span class="preprocessor">#define SMC_PMCTRL_VALUE 0x00u         </span><span class="comment">/* SMC_PMCTRL */</span><span class="preprocessor"></span></div><div class="line"><a name="l00229"></a><span class="lineno">  229</span>&#160;<span class="comment">/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */</span></div><div class="line"><a name="l00230"></a><span class="lineno">  230</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_CLKDIV1_VALUE 0x00u </span><span class="comment">/* SIM_CLKDIV1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00231"></a><span class="lineno">  231</span>&#160;<span class="comment">/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */</span></div><div class="line"><a name="l00232"></a><span class="lineno">  232</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u </span><span class="comment">/* SIM_SOPT1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00233"></a><span class="lineno">  233</span>&#160;<span class="comment">/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */</span></div><div class="line"><a name="l00234"></a><span class="lineno">  234</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT2_VALUE 0x02000000u </span><span class="comment">/* SIM_SOPT2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00235"></a><span class="lineno">  235</span>&#160;<span class="preprocessor">#elif(CLOCK_SETUP == 3)</span></div><div class="line"><a name="l00236"></a><span class="lineno">  236</span>&#160;<span class="preprocessor">#define DEFAULT_SYSTEM_CLOCK 2000000u     </span><span class="comment">/* Default System clock value */</span><span class="preprocessor"></span></div><div class="line"><a name="l00237"></a><span class="lineno">  237</span>&#160;<span class="preprocessor">#define CPU_INT_SLOW_CLK_HZ 2000000u      </span><span class="comment">/* Value of the slow internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00238"></a><span class="lineno">  238</span>&#160;<span class="preprocessor">#define MCG_MODE MCG_MODE_LIRC_2M         </span><span class="comment">/* Clock generator mode */</span><span class="preprocessor"></span></div><div class="line"><a name="l00239"></a><span class="lineno">  239</span>&#160;<span class="comment">/* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */</span></div><div class="line"><a name="l00240"></a><span class="lineno">  240</span>&#160;<span class="preprocessor">#define MCG_C1_VALUE 0x42u                </span><span class="comment">/* MCG_C1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00241"></a><span class="lineno">  241</span>&#160;<span class="comment">/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */</span></div><div class="line"><a name="l00242"></a><span class="lineno">  242</span>&#160;<span class="preprocessor">#define MCG_C2_VALUE 0x00u                </span><span class="comment">/* MCG_C2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00243"></a><span class="lineno">  243</span>&#160;<span class="comment">/* MCG_SC: FCRDIV=0 */</span></div><div class="line"><a name="l00244"></a><span class="lineno">  244</span>&#160;<span class="preprocessor">#define MCG_SC_VALUE 0x00u                </span><span class="comment">/* MCG_SC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00245"></a><span class="lineno">  245</span>&#160;<span class="comment">/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */</span></div><div class="line"><a name="l00246"></a><span class="lineno">  246</span>&#160;<span class="preprocessor">#define MCG_MC_VALUE 0x00u                </span><span class="comment">/* MCG_MC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00247"></a><span class="lineno">  247</span>&#160;<span class="comment">/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */</span></div><div class="line"><a name="l00248"></a><span class="lineno">  248</span>&#160;<span class="preprocessor">#define OSC0_CR_VALUE 0x00u               </span><span class="comment">/* OSC0_CR */</span><span class="preprocessor"></span></div><div class="line"><a name="l00249"></a><span class="lineno">  249</span>&#160;<span class="comment">/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */</span></div><div class="line"><a name="l00250"></a><span class="lineno">  250</span>&#160;<span class="preprocessor">#define SMC_PMCTRL_VALUE 0x00u            </span><span class="comment">/* SMC_PMCTRL */</span><span class="preprocessor"></span></div><div class="line"><a name="l00251"></a><span class="lineno">  251</span>&#160;<span class="comment">/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */</span></div><div class="line"><a name="l00252"></a><span class="lineno">  252</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u </span><span class="comment">/* SIM_CLKDIV1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00253"></a><span class="lineno">  253</span>&#160;<span class="comment">/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */</span></div><div class="line"><a name="l00254"></a><span class="lineno">  254</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u </span><span class="comment">/* SIM_SOPT1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00255"></a><span class="lineno">  255</span>&#160;<span class="comment">/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */</span></div><div class="line"><a name="l00256"></a><span class="lineno">  256</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u </span><span class="comment">/* SIM_SOPT2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00257"></a><span class="lineno">  257</span>&#160;<span class="preprocessor">#elif(CLOCK_SETUP == 4)</span></div><div class="line"><a name="l00258"></a><span class="lineno">  258</span>&#160;<span class="preprocessor">#define DEFAULT_SYSTEM_CLOCK 2000000u     </span><span class="comment">/* Default System clock value */</span><span class="preprocessor"></span></div><div class="line"><a name="l00259"></a><span class="lineno">  259</span>&#160;<span class="preprocessor">#define CPU_INT_SLOW_CLK_HZ 8000000u      </span><span class="comment">/* Value of the slow internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00260"></a><span class="lineno">  260</span>&#160;<span class="preprocessor">#define MCG_MODE MCG_MODE_LIRC_2M         </span><span class="comment">/* Clock generator mode */</span><span class="preprocessor"></span></div><div class="line"><a name="l00261"></a><span class="lineno">  261</span>&#160;<span class="comment">/* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */</span></div><div class="line"><a name="l00262"></a><span class="lineno">  262</span>&#160;<span class="preprocessor">#define MCG_C1_VALUE 0x02u                </span><span class="comment">/* MCG_C1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00263"></a><span class="lineno">  263</span>&#160;<span class="comment">/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */</span></div><div class="line"><a name="l00264"></a><span class="lineno">  264</span>&#160;<span class="preprocessor">#define MCG_C2_VALUE 0x01u                </span><span class="comment">/* MCG_C2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00265"></a><span class="lineno">  265</span>&#160;<span class="comment">/* MCG_SC: FCRDIV=0 */</span></div><div class="line"><a name="l00266"></a><span class="lineno">  266</span>&#160;<span class="preprocessor">#define MCG_SC_VALUE 0x00u                </span><span class="comment">/* MCG_SC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00267"></a><span class="lineno">  267</span>&#160;<span class="comment">/* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */</span></div><div class="line"><a name="l00268"></a><span class="lineno">  268</span>&#160;<span class="preprocessor">#define MCG_MC_VALUE 0x80u                </span><span class="comment">/* MCG_MC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00269"></a><span class="lineno">  269</span>&#160;<span class="comment">/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */</span></div><div class="line"><a name="l00270"></a><span class="lineno">  270</span>&#160;<span class="preprocessor">#define OSC0_CR_VALUE 0x00u               </span><span class="comment">/* OSC0_CR */</span><span class="preprocessor"></span></div><div class="line"><a name="l00271"></a><span class="lineno">  271</span>&#160;<span class="comment">/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */</span></div><div class="line"><a name="l00272"></a><span class="lineno">  272</span>&#160;<span class="preprocessor">#define SMC_PMCTRL_VALUE 0x00u            </span><span class="comment">/* SMC_PMCTRL */</span><span class="preprocessor"></span></div><div class="line"><a name="l00273"></a><span class="lineno">  273</span>&#160;<span class="comment">/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */</span></div><div class="line"><a name="l00274"></a><span class="lineno">  274</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u </span><span class="comment">/* SIM_CLKDIV1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00275"></a><span class="lineno">  275</span>&#160;<span class="comment">/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */</span></div><div class="line"><a name="l00276"></a><span class="lineno">  276</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u </span><span class="comment">/* SIM_SOPT1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00277"></a><span class="lineno">  277</span>&#160;<span class="comment">/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */</span></div><div class="line"><a name="l00278"></a><span class="lineno">  278</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT2_VALUE 0x03040000u </span><span class="comment">/* SIM_SOPT2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00279"></a><span class="lineno">  279</span>&#160;<span class="preprocessor">#elif(CLOCK_SETUP == 5)</span></div><div class="line"><a name="l00280"></a><span class="lineno">  280</span>&#160;<span class="preprocessor">#define DEFAULT_SYSTEM_CLOCK 2000000u     </span><span class="comment">/* Default System clock value */</span><span class="preprocessor"></span></div><div class="line"><a name="l00281"></a><span class="lineno">  281</span>&#160;<span class="preprocessor">#define CPU_INT_SLOW_CLK_HZ 2000000u      </span><span class="comment">/* Value of the slow internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00282"></a><span class="lineno">  282</span>&#160;<span class="preprocessor">#define MCG_MODE MCG_MODE_LIRC_2M         </span><span class="comment">/* Clock generator mode */</span><span class="preprocessor"></span></div><div class="line"><a name="l00283"></a><span class="lineno">  283</span>&#160;<span class="comment">/* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */</span></div><div class="line"><a name="l00284"></a><span class="lineno">  284</span>&#160;<span class="preprocessor">#define MCG_C1_VALUE 0x80u                </span><span class="comment">/* MCG_C1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00285"></a><span class="lineno">  285</span>&#160;<span class="comment">/* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */</span></div><div class="line"><a name="l00286"></a><span class="lineno">  286</span>&#160;<span class="preprocessor">#define MCG_C2_VALUE 0x15u                </span><span class="comment">/* MCG_C2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00287"></a><span class="lineno">  287</span>&#160;<span class="comment">/* MCG_SC: FCRDIV=0 */</span></div><div class="line"><a name="l00288"></a><span class="lineno">  288</span>&#160;<span class="preprocessor">#define MCG_SC_VALUE 0x00u                </span><span class="comment">/* MCG_SC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00289"></a><span class="lineno">  289</span>&#160;<span class="comment">/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */</span></div><div class="line"><a name="l00290"></a><span class="lineno">  290</span>&#160;<span class="preprocessor">#define MCG_MC_VALUE 0x00u                </span><span class="comment">/* MCG_MC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00291"></a><span class="lineno">  291</span>&#160;<span class="comment">/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */</span></div><div class="line"><a name="l00292"></a><span class="lineno">  292</span>&#160;<span class="preprocessor">#define OSC0_CR_VALUE 0x80u               </span><span class="comment">/* OSC0_CR */</span><span class="preprocessor"></span></div><div class="line"><a name="l00293"></a><span class="lineno">  293</span>&#160;<span class="comment">/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */</span></div><div class="line"><a name="l00294"></a><span class="lineno">  294</span>&#160;<span class="preprocessor">#define SMC_PMCTRL_VALUE 0x00u            </span><span class="comment">/* SMC_PMCTRL */</span><span class="preprocessor"></span></div><div class="line"><a name="l00295"></a><span class="lineno">  295</span>&#160;<span class="comment">/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */</span></div><div class="line"><a name="l00296"></a><span class="lineno">  296</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u </span><span class="comment">/* SIM_CLKDIV1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00297"></a><span class="lineno">  297</span>&#160;<span class="comment">/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */</span></div><div class="line"><a name="l00298"></a><span class="lineno">  298</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u </span><span class="comment">/* SIM_SOPT1 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00299"></a><span class="lineno">  299</span>&#160;<span class="comment">/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */</span></div><div class="line"><a name="l00300"></a><span class="lineno">  300</span>&#160;<span class="preprocessor">#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u </span><span class="comment">/* SIM_SOPT2 */</span><span class="preprocessor"></span></div><div class="line"><a name="l00301"></a><span class="lineno">  301</span>&#160;<span class="preprocessor">#else</span></div><div class="line"><a name="l00302"></a><span class="lineno">  302</span>&#160;<span class="preprocessor">#error The selected clock setup is not supported.</span></div><div class="line"><a name="l00303"></a><span class="lineno">  303</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* (CLOCK_SETUP == 5) */</span><span class="preprocessor"></span></div><div class="line"><a name="l00304"></a><span class="lineno">  304</span>&#160;<span class="preprocessor">#else</span></div><div class="line"><a name="l00305"></a><span class="lineno">  305</span>&#160;<span class="preprocessor">#define DEFAULT_SYSTEM_CLOCK 8000000u </span><span class="comment">/* Default System clock value */</span><span class="preprocessor"></span></div><div class="line"><a name="l00306"></a><span class="lineno">  306</span>&#160;<span class="preprocessor">#define CPU_INT_SLOW_CLK_HZ 8000000u  </span><span class="comment">/* Value of the slow internal oscillator clock frequency in Hz  */</span><span class="preprocessor"></span></div><div class="line"><a name="l00307"></a><span class="lineno">  307</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00308"></a><span class="lineno">  308</span>&#160;</div><div class="line"><a name="l00318"></a><span class="lineno">  318</span>&#160;<span class="keyword">extern</span> uint32_t SystemCoreClock;</div><div class="line"><a name="l00319"></a><span class="lineno">  319</span>&#160;</div><div class="line"><a name="l00327"></a><span class="lineno">  327</span>&#160;<span class="keywordtype">void</span> SystemInit(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00328"></a><span class="lineno">  328</span>&#160;</div><div class="line"><a name="l00336"></a><span class="lineno">  336</span>&#160;<span class="keywordtype">void</span> SystemCoreClockUpdate(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00337"></a><span class="lineno">  337</span>&#160;</div><div class="line"><a name="l00338"></a><span class="lineno">  338</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00339"></a><span class="lineno">  339</span>&#160;}</div><div class="line"><a name="l00340"></a><span class="lineno">  340</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00341"></a><span class="lineno">  341</span>&#160;</div><div class="line"><a name="l00342"></a><span class="lineno">  342</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* #if !defined(_SYSTEM_MKL43Z4_H_) */</span><span class="preprocessor"></span></div></div><!-- fragment --></div><!-- contents -->
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